As integrated circuit devices are scaled down to finer and finer geometries, reduction of resistance within interconnect lines is essential if signal propagation delay is to be minimized so that component speeds may increase. Originally, field-effect transistors were truly metal-oxide-silicon (MOS) devices. However, the aluminum metal used for transistor gates and interconnect lines was incompatible with the high temperatures (around 1,000.degree. C.) required to drive self-aligned source/drain implants into the silicon substrate. As a consequence, conductively-doped polycrystalline silicon (hereinafter, also "poly") soon replaced metallic aluminum as the primary gate and interconnect material. However, doped poly possesses far greater electrical resistance (around 20 ohms/square) than aluminum metal (approximately 0.030 ohms/square), and as device dimensions have been scaled down, the higher resistance of doped poly has become a performance limiting factor.
A number of techniques have been tried in attempts to reduce the sheet resistance of polycrystalline silicon. One of the more promising techniques involves the creation of a refractory metal silicide layer on top of the doped poly layer. A refractory metal is normally deemed to be a metal chosen from the group consisting of tungsten, molybdenum, cobalt and titanium. A refractory metal silicide may be created either by depositing one of the refractory metals on top of the poly layer and allowing it to react with the poly at elevated temperature or by depositing the refractory metal silicide directly on the poly layer. The sheet resistance of a poly layer, when coated with tungsten silicide for example, is reduced to only 5-7 ohms/square. Although it is conceivable to eliminate the poly layer altogether and use only the refractory metal silicide for transistor gates and interconnect lines, this is generally not advisable because transistor work function is altered.
For the sake of simplification, this document will, henceforth, discuss only the use of tungsten silicide (WSi.sub.x). However, the same steps that are taken to protect a tungsten silicide layer may be used to protect a silicide layer of molybdenum, cobalt or titanium.
FIG. 1 is a cross-sectional drawing of a DRAM cell, employing conventional poly-tungsten silicide technology, undergoing fabrication during the gate and word line patterning stage. This cell uses conventional polycrystalline silicon-tungsten silicide technology. The cell is constructed on a lightly-doped p-type substrate 11. Field oxide regions 12 provide electrical isolation between individual cells within the array. A pad oxide layer 13 is grown on the surface of the entire wafer, followed by the blanket deposition of a poly layer 14 approximately 4,000 angstroms in thickness. Following the blanket deposition of a 1,000 angstrom-thick tungsten silicide layer 15, a patterning photoresist mask 16 is used to pattern future transistor gates and word lines.
Referring now to FIG. 2, which is a crosssection of the DRAM cell of FIG. 1 following a series of conventional etch steps, field-effect transistor gate 21 and word line 22 are fully formed and photoresist mask 16 has been removed.
The use of tungsten silicide-coated poly, though, is not without its problems. One of the problems is that the silicon and tungsten atoms within the tungsten silicide layer apparently react with oxygen (creating tungsten oxide and silicon oxide) during the silicide annealing step and other subsequent high-temperature fabrication steps. The same oxidation phenomena also afflicts silicides of molybdenum, cobalt, and titanium. Since tungsten oxide and silicon oxide are both excellent dielectrics, the effectiveness of the tungsten silicide layer is reduced. FIG. 3, a 35,000.times.photomicrograph of a conventional poly-silicide field-effect transistor gate, is representative of a "best-case" scenario using the conventional polysilicide process. The gate, comprised of a poly layer 14 and a tungsten silicide layer 15 has been oxidized, along with the underlying silicon substrate 11, forming a thin-spacer silicon oxide layer 31 that is used to self-align lightly-doped drain and source implants. A region 32 comprised of both silicon and tungsten oxide is visible in this photograph. Although it is sometimes possible to eliminate oxygen from the processing environment during high-temperature exposure, it is often impossible or impractical to do so.
Another problem is the mechanical instability of the tungsten silicide layer. During high-temperature processing, the layer may lift, thereby eliminating its reduced resistance effect on the poly layer. This is especially true where process variations result in offset etches. FIG. 4, a 20,200.times.photomicrograph, is a cross section of a pair of adjacent DRAM cells. The tungsten silicide on both transistor gates 41 has lifted and oxidized to form popcorn-like structures 42. FIG. 5, a 15,000.times.photomicrograph, is a top perspective view of a portion of a partially-fabricated DRAM array. The tungsten silicide layer on each of the three visible word lines 41 has become partially detached from the underlying poly layer 42, resulting in the fluffy structures 43 crowning each line.
As a result of the aforementioned problems encountered with tungsten silicide, attempts have been made to protect tungsten silicide layers with an oxygen-impermeable silicon nitride coating. However, this approach has not been very successful due to the differences in the expansion coefficients of the two materials. As a result of the mechanical stresses generated at the interface between the silicide and the nitride, the nitride will often peel away from the tungsten silicide layer in flakes, thus terminating the antioxidation protection and resulting in intense nitride particle contamination on the wafer.
What is needed is a process that will reduce the stresses generated between a nitride layer and an underlying tungsten silicide layer that is, in turn, deposited on an underlying poly layer, so that the nitride will remain bonded to the tungsten silicide layer.